The switched mode power supply (SMPS) is a well-known type of power converter having a diverse range of applications by virtue of its small size and weight and high efficiency, for example in personal computers and portable electronic devices such as cell phones. A SMPS achieves these advantages by switching one or more switching elements such as power MOSFETs at a high frequency (usually tens to hundreds of kHz), with the frequency or duty cycle of the switching being adjusted by a feedback loop (also widely referred to as a “compensation loop” or “feedback circuit”) to convert an input voltage to a desired output voltage. A SMPS may take the form of a rectifier (AC/DC converter), a DC/DC converter, a frequency changer (AC/AC) or an inverter (DC/AC).
The feedback loop of a conventional SMPS 10 is illustrated in FIG. 1A. The feedback loop comprises an error signal generator 20 arranged to generate an error signal indicative of the difference between the output voltage, Vout, of the SMPS 10 and a reference voltage, Vref. The error signal is then sampled by the sample and hold (S&H) circuit 30. The feedback look also has a controller 40 that generates, based on the sampled error signal and in accordance with a control law defined by one or more control law parameters, a control signal D that can be used for regulating the switching frequency or the switching duty cycle of the switching element(s) in the powertrain 50 of the SMPS 10, to keep the output voltage Vout in the vicinity of a predetermined value. The controller 40 may, as in the present example, be a Proportional-Integral-Derivative (PID) controller that regulates the duty cycle (or the switching frequency, as the case may be) of the switching element(s) to keep the output voltage of the SMPS 10 substantially constant, in accordance with a PID control law that is characterised by the values of the P, I and D control parameters set in the PID controller.
Variations in the input voltage Vin of the SMPS 10 may (depending on the time scales over which they occur) be manifested as variations in the output voltage Vout of the SMPS 10. To suppress deviations in the output voltage Vout caused by input voltage fluctuations, a conventional SMPS typically employs a Voltage Feed-Forward (VFF) mechanism to adjust the control signal D based on the input voltage Vin. In the example of FIG. 1A, the VFF mechanism comprises a VFF scaling block 60 arranged to scale the control signal D from the controller 40 by a scaling factor that is based on Vin to generate a scaled control signal, Dscale. The VFF mechanism thus allows the feedback loop of the SMPS 10 to respond quickly to changes in Vin, without relying on the manifestation of these changes in the output of the SMPS 10, thereby allowing the SMPS 10 to suppress transients in the input voltage effectively, with relatively little delay.
The conventional SMPS of FIG. 1A makes use of a periodic reference signal Sref and the scaled duty cycle control signal Dscale to generate drive signals Qi for turning ON and OFF the switching element(s) in its powertrain 50. In the so-called Nyquist-sampled controller, in which the output voltage sampling rate and the SMPS switching frequency fSW are the same, a duty cycle control signal indicative of a duty cycle value is generated during one period of the reference signal Sref, using a sample of the output voltage Vout obtained during this period, and is then used to control the switching of the switching element(s) in the next period. A conventional SMPS typically uses pulse width modulation (PWM) to generate drive signals for the switching element(s), wherein the duty cycle control signal Dscale is compared with the reference signal Sref, and the state of the switching element(s) is controlled on the basis of that comparison.
The SMPS may, as in the example of FIG. 1A, employ a digital PWM (DPWM) 70 to drive the switching element(s) based on a comparison between the reference signal Sref and the scaled duty cycle control signal Dscale. For example, where the SMPS employs dual-edge modulation, the reference signal Sref may, as shown in FIG. 1B, be provided in the form of a triangular waveform. In FIG. 1B, the value, S1, of the scaled duty cycle control signal Sscale that is to be used in the period P1 (starting at time t=T1) is generated during the period P0. The DPWM 70 compares Sscale with Sref and generates a drive signal, Sdrive, for the switching element(s) based on that comparison. In the example of FIG. 1B, the drive signal Sdrive is high, and the switching element(s) are consequently turned ON, when Sscale exceeds Sref.
In the conventional SMPS described above, there is a delay of about one period of the reference signal Sref between the calculation of the duty cycle control signal value and the switching of the switching element(s) in accordance with that value. This delay leads to a phase loss that reduces the performance of the SMPS 10, for example, in terms of load transient response.
Due to the relatively high power consumption and silicon area of fast Analog to Digital Converters (ADC) and fast digital signal processing (DSP) circuits that have been available in the past, SMPS controllers of the conventional type described above have continued to be the industry standard, despite the performance limitations outlined above. However, technological improvements in the field of CMOS processes, which allow high-speed ADC and high-speed DSP to be realised, have opened up the possibility of improving SMPS performance at an affordable cost. More particularly, the so-called multi-rate controllers that have been developed sample the feedback signal (e.g. an error signal indicative of the difference between the output voltage and a reference signal) at a frequency N times higher than the reference signal frequency, and use this oversampled signal together with one or more other signals sampled at lower frequency to switch the switching element(s) multiple times during each period of the reference signal (rather than once, as in the case of the conventional SMPS whose operation is illustrated in FIG. 1B), thereby reducing the aforementioned phase loss.
To achieve a good feedback loop response and avoid oscillations, multi-rate SMPS controllers typically employ a filtering process that attenuates the usual voltage ripple which propagates to the feedback loop from the output of the SMPS. The voltage ripple is a substantially periodic oscillation in the output voltage of the SMPS, which is typically small in relation to the output voltage, and which may occur as a result of an incomplete suppression of an output alternating waveform by the SMPS's output filter. Conventional digital SMPS controllers usually attenuate the ripple component by oversampling the output voltage of the SMPS (or the error signal, as the case may be) and manipulating the oversampled signal using an appropriately configured Finite Impulse Response (FIR) or Infinite Impulse Response (IIR) filter, e.g. a moving average filter or a decimation filter. Such filtering processes cause the voltage ripple component of the oversampled signal to be suppressed, thus allowing the low-bandwidth signal (i.e. voltage deviations due to transients) to be obtained for use in output voltage regulation.